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40-Channel, 3 V/5 V, Single-Supply, Serial, 14-Bit Voltage Output DAC AD5384
FEATURES
Guaranteed monotonic INL error: 4 LSB max On-chip 1.25 V/2.5 V, 10 ppm/C reference Temperature range: -40C to +85C Rail-to-rail output amplifier Power-down Package type: 100-lead CSPBGA (10 mm x 10 mm) User Interfaces: Serial (SPI-(R)/QSPI-TM/MICROWIRE-TM/DSP-compatible, featuring data readback) I2C-(R)compatible
INTEGRATED FUNCTIONS
Channel monitor Simultaneous output update via LDAC Clear function to user-programmable code Amplifier boost mode to optimize slew rate User-programmable offset and gain adjust Toggle mode enables square wave generation Thermal monitor
APPLICATIONS
Variable optical attenuators (VOA) Level setting (ATE) Optical micro-electro-mechanical systems (MEMS) Control systems Instrumentation
FUNCTIONAL BLOCK DIAGRAM
DVDD (x3) PD SYNC/AD 0 DCEN/AD 1 DGND (x4) AVDD (x5) AGND (x5) DAC GND (x5) REFGND REFOUT/REFIN SIGNAL GND (x5)
AD5384
1.25V/2.5V REFERENCE
14
INPUT 14 REG 0 14 m REG 0 c REG 0
14
DAC 14 REG 0
DAC 0 VOUT0
SDO DIN/SDA SCLK/SCL SPI/I2C INTERFACE CONTROL LOGIC STATE MACHINE + CONTROL LOGIC
14
R R
14
INPUT 14 REG 1 14 14 m REG 1 c REG 1
14
DAC 14 REG 1
DAC 1 VOUT1 VOUT2 R R VOUT4 VOUT3
14 RESET BUSY CLR VOUT0......VOUT38 14 POWER-ON RESET
INPUT 14 REG 6 14 14 m REG 6 c REG 6
14
DAC 14 REG 6
DAC 6
VOUT5 VOUT6
R R
INPUT 14 REG 7 14 m REG 7 c REG 7
14
DAC 14 REG 7
DAC 7 VOUT7 VOUT8 R R
04652-0-001
39-TO-1 MUX
14
x5
VOUT39/MON_OUT LDAC
VOUT38
Figure 1. Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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AD5384 TABLE OF CONTENTS
General Description ......................................................................... 3 Specifications..................................................................................... 4 AD5384-5 Specifications ............................................................. 4 AC Characteristics........................................................................ 6 AD5384-3 Specifications ............................................................. 7 AC Characteristics........................................................................ 9 Timing Characteristics................................................................... 10 Serial Interface ............................................................................ 10 I2C Serial Interface...................................................................... 12 Absolute Maximum Ratings.......................................................... 13 Pin Configuration and Function Descriptions........................... 14 Terminology .................................................................................... 17 Typical Performance Characteristics ........................................... 18 Functional Description .................................................................. 21 DAC Architecture--General..................................................... 21 Data Decoding ............................................................................ 21 On-Chip Special Function Registers (SFR) ............................ 22 SFR Commands .......................................................................... 22 Hardware Functions....................................................................... 25 Reset Function ............................................................................ 25 Asynchronous Clear Function.................................................. 25 BUSY and LDAC Functions...................................................... 25 Power-On Reset.......................................................................... 25 Power-Down ............................................................................... 25 Interfaces.......................................................................................... 26 DSP-, SPI-, Microwire-Compatible Serial Interfaces ............ 26 I2C Serial Interface ..................................................................... 28 Microprocessor Interfacing....................................................... 31 Application Information................................................................ 32 Power Supply Decoupling ......................................................... 32 Monitor Function....................................................................... 32 Toggle Mode Function............................................................... 32 Thermal Monitor Function....................................................... 33 AD5384 in a MEMS-Based Optical Switch ............................ 33 Optical Attenuators.................................................................... 34 Outline Dimensions ....................................................................... 35 Ordering Guide .......................................................................... 35
REVISION HISTORY
10/04--Changed from Rev. 0 to Rev. A Changes to Table 19........................................................................ 24 Changes to Ordering Guide .......................................................... 35 7/04--Revision 0: Initial Version
Rev. A | Page 2 of 36
AD5384 GENERAL DESCRIPTION
The AD5384 is a complete single-supply, 40-channel, 14-bit DAC available in a 100-lead CSPBGA package. All 40 channels have an on-chip output amplifier with rail-to-rail operation. The AD5384 includes an internal 1.25 V/2.5 V, 10 ppm/C reference, an on-chip channel monitor function that multiplexes the analog outputs to a common MON_OUT pin for external monitoring, and an output amplifier boost mode that allows the amplifier slew rate to be optimized. The AD5384 contains a serial interface compatible with SPI, QSPI, MICROWIRE, and DSP interface standards with interface speeds in excess of 30 MHz and an I2C-compatible interface supporting 400 kHz data transfer rate. An input register followed by a DAC register provides double buffering, allowing the DAC outputs to be updated independently or simultaneously. using the LDAC input. Each channel has a programmable gain and offset adjust register letting the user fully calibrate any DAC channel. Power consumption is typically 0.25 mA/channel with boost mode off.
Table 1. Complete Family of High Channel Count, Low Voltage, Single-Supply DACs in Portfolio
Model AD5380BST-5 AD5380BST-3 AD5381BST-5 AD5381BST-3 AD5384BBC-5 AD5384BBC-3 AD5382BST-5 AD5382BST-3 AD5383BST-5 AD5383BST-3 AD5390BST-5 AD5390BCP-5 AD5390BST-3 AD5390BCP-3 AD5391BST-5 AD5391BCP-5 AD5391BST-3 AD5391BCP-3 AD5392BST-5 AD5392BCP-5 AD5392BST-3 AD5392BCP-3 Resolution 14 Bits 14 Bits 12 Bits 12 Bits 14 Bits 14 Bits 14 Bits 14 Bits 12 Bits 12 Bits 14 Bits 14 Bits 14 Bits 14 Bits 12 Bits 12 Bits 12 Bits 12 Bits 14 Bits 14 Bits 14 Bits 14 Bits AVDD Range 4.5 V to 5.5 V 2.7 V to 3.6 V 4.5 V to 5.5 V 2.7 V to 3.6 V 4.5 V to 5.5 V 2.7 V to 3.6 V 4.5 V to 5.5 V 2.7 V to 3.6 V 4.5 V to 5.5 V 2.7 V to 3.6 V 4.5 V to 5.5 V 4.5 V to 5.5 V 2.7 V to 3.6 V 2.7 V to 3.6 V 4.5 V to 5.5 V 4.5 V to 5.5 V 2.7 V to 3.6 V 2.7 V to 3.6 V 4.5 V to 5.5 V 4.5 V to 5.5 V 2.7 V to 3.6 V 2.7 V to 3.6 V Output Channels 40 40 40 40 40 40 32 32 32 32 16 16 16 16 16 16 16 16 8 8 8 8 Linearity Error (LSB) 4 4 1 1 4 4 4 4 1 1 3 3 4 4 1 1 1 1 3 3 4 4 Package Description 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead CSPBGA 100-Lead CSPBGA 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 52-Lead LQFP 64-Lead LFCSP 52-Lead LQFP 64-Lead LFCSP 52-Lead LQFP 64-Lead LFCSP 52-Lead LQFP 64-Lead LFCSP 52-Lead LQFP 64-Lead LFCSP 52-Lead LQFP 64-Lead LFCSP Package Option ST-100 ST-100 ST-100 ST-100 BC-100 BC-100 ST-100 ST-100 ST-100 ST-100 ST-52 CP-64 ST-52 CP-64 ST-52 CP-64 ST-52 CP-64 ST-52 CP-64 ST-52 CP-64
Table 2. 40-Channel, Bipolar Voltage Output DAC
Model AD5379ABC Resolution 14 Bits Analog Supplies 11.4 V to 16.5 V Output Channels 40 Linearity Error (LSB) 3 Package 108-Lead CSPBGA Package Option BC-108
Rev. A | Page 3 of 36
AD5384 SPECIFICATIONS
AD5384-5 SPECIFICATIONS
AVDD = 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V; external REFIN = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3.
Parameter ACCURACY Resolution Relative Accuracy2 (INL) Differential Nonlinearity (DNL) Zero-Scale Error Offset Error Offset Error TC Gain Error Gain Temperature Coefficient3 DC Crosstalk3 REFERENCE INPUT/OUTPUT Reference Input3 Reference Input Voltage DC Input Impedance Input Current Reference Range Reference Output4 Output Voltage Reference TC OUTPUT CHARACTERISTICS3 Output Voltage Range2 Short-Circuit Current Load Current Capacitive Load Stability RL = RL = 5 k DC Output Impedance MONITOR PIN Output Impedance Three-State Leakage Current LOGIC INPUTS (EXCEPT SDA/SCL)3 VIH, Input High Voltage VIL, Input Low Voltage Input Current Pin Capacitance LOGIC INPUTS (SDA, SCL ONLY) VIH, Input High Voltage VIL, Input Low Voltage IIN, Input Leakage Current VHYST, Input Hysteresis CIN, Input Capacitance Glitch Rejection AD5384-51 14 4 -1/+2 4 4 5 0.024 0.06 2 0.5 Unit Bits LSB max LSB max mV max mV max V/C typ % FSR max % FSR max ppm FSR/C typ LSB max Test Conditions/Comments
1 LSB typical Guaranteed monotonic by design over temperature Measured at code 32 in the linear region At 25C TMIN to TMAX
2.5 1 1 1 to VDD/2
V M min A max V min/max
1% for specified performance, AVDD = 2 x REFIN + 50 mV Typically 100 M Typically 30 nA Enabled via CR10 in the AD5384 control register, CR12, selects the output voltage. At ambient; CR12 = 1; optimized for 2.5 V operation CR12 = 0 Temperature range: +25C to +85C Temperature range: -40C to +85C
2.495/2.505 1.22/1.28 10 15 0/AVDD 40 1 200 1000 0.5 500 100 2 0.8 10 10 0.7 DVDD 0.3 DVDD 1 0.05 DVDD 8 50
V min/max V min/max ppm/C max ppm/C max V min/max mA max mA max pF max pF max max typ nA typ
DVDD = 2.7 V to 5.5 V V min V max A max pF max V min V max A max V min pF typ ns max
Rev. A | Page 4 of 36
Total for all pins. TA = TMIN to TMAX
SMBus-compatible at DVDD < 3.6 V SMBus-compatible at DVDD < 3.6 V
Input filtering suppresses noise spikes of less than 50 ns
AD5384
Parameter LOGIC OUTPUTS (BUSY, SDO)3 VOL, Output Low Voltage VOH, Output High Voltage VOL, Output Low Voltage VOH, Output High Voltage High Impedance Leakage Current High Impedance Output Capacitance LOGIC OUTPUT (SDA)3 VOL, Output Low Voltage Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS AVDD DVDD Power Supply Sensitivity3 Midscale/VDD AIDD DIDD AIDD (Power-Down) DIDD (Power-Down) Power Dissipation AD5384-51 0.4 DVDD - 1 0.4 DVDD - 0.5 1 5 0.4 0.6 1 8 4.5/5.5 2.7/5.5 -85 0.375 0.475 1 2 20 80 Unit V max V min V max V min A max pF typ V max V max A max pF typ V min/max V min/max dB typ mA/channel max mA/channel max mA max A max A max mW max Test Conditions/Comments DVDD = 5 V 10%, sinking 200 A DVDD = 5 V 10%, sourcing 200 A DVDD = 2.7 V to 3.6 V, sinking 200 A DVDD = 2.7 V to 3.6 V, sourcing 200 A SDO only SDO only ISINK = 3 mA ISINK = 6 mA
Outputs unloaded, boost off; 0.25 mA/channel typ Outputs unloaded, boost on; 0.32 5mA/channel typ VIH = DVDD, VIL = DGND Typically 200 nA Typically 3 A Outputs unloaded, boost off, AVDD = DVDD = 5 V
1 2
AD5384-5 is calibrated using an external 2.5 V reference. Temperature range for all versions: -40C to +85C. Accuracy guaranteed from VOUT = 10 mV to AVDD - 50 mV. 3 Guaranteed by characterization, not production tested. 4 Default on the AD5384-5 is 2.5 V. Programmable to 1.25 V via CR12 in the AD5384 control register; operating the AD5384-5 with a 1.25 V reference will lead to degraded accuracy specifications.
Rev. A | Page 5 of 36
AD5384
AC CHARACTERISTICS1
AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V. Table 4.
Parameter DYNAMIC PERFORMANCE Output Voltage Settling Time 8 10 2 3 12 15 100 1 0.8 0.1 15 40 150 100 s typ s max V/s typ V/s typ nV-s typ mV typ dB typ nV-s typ nV-s typ nV-s typ V p-p typ V p-p typ nV/Hz typ nV/Hz typ AD5384-5 Unit Test Conditions/Comments Boost mode off, CR11 = 0 1/4 scale to 3/4 scale change settling to 1 LSB
Slew Rate2 Digital-to-Analog Glitch Energy Glitch Impulse Peak Amplitude Channel-to-Channel Isolation DAC-to-DAC Crosstalk Digital Crosstalk Digital Feedthrough Output Noise 0.1 Hz to 10 Hz Output Noise Spectral Density @ 1 kHz @ 10 kHz
Boost mode off, CR11 = 0 Boost mode on, CR11 = 1
See the Terminology section See the Terminology section Effect of input bus activity on DAC output under test External reference, midscale loaded to DAC Internal reference, midscale loaded to DAC
1 2
Guaranteed by design and characterization, not production tested. The slew rate can be programmed via the current boost control bit (CR11) in the AD5384 control register.
Rev. A | Page 6 of 36
AD5384
AD5384-3 SPECIFICATIONS
AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V; external REFIN = 1.25 V; all specifications TMIN to TMAX, unless otherwise noted. Table 5.
Parameter ACCURACY Resolution Relative Accuracy2 Differential Nonlinearity Zero-Scale Error Offset Error Offset Error TC Gain Error Gain Temperature Coefficient3 DC Crosstalk3 REFERENCE INPUT/OUTPUT Reference Input3 Reference Input Voltage DC Input Impedance Input Current Reference Range Reference Output4 Output Voltage Reference TC OUTPUT CHARACTERISTICS3 Output Voltage Range2 Short-Circuit Current Load Current Capacitive Load Stability RL = RL = 5 k DC Output Impedance MONITOR PIN Output Impedance Three-State Leakage Current LOGIC INPUTS (EXCEPT SDA/SCL)3 VIH, Input High Voltage VIL, Input Low Voltage Input Current Pin Capacitance LOGIC INPUTS (SDA, SCL ONLY) VIH, Input High Voltage VIL, Input Low Voltage IIN, Input Leakage Current VHYST, Input Hysteresis CIN, Input Capacitance Glitch Rejection AD5384-31 14 4 -1/+2 4 4 5 0.024 0.1 2 0.5 Unit Bits LSB max LSB max mV max mV max V/C typ % FSR max % FSR max ppm FSR/C typ LSB max Test Conditions/Comments
Guaranteed monotonic over temperature Measured at Code 64 in the linear region At 25C TMIN to TMAX
1.25 1 1 1 to AVDD/2 1.245/1.255 2.47/2.53 10 15 0/AVDD 40 1 200 1000 0.5 500 100 2 0.8 10 10 0.7 DVDD 0.3 DVDD 1 0.05 DVDD 8 50
V M min A max V min/max V min/max V min/max ppm/C max ppm/C max V min/max mA max mA max pF max pF max max typ nA typ
1% for specified performance Typically 100 M Typically 30 nA
At ambient; CR12 = 0; optimized for 1.25 V operation CR12 = 1 Temperature range: +25C to +85C Temperature range: -40C to +85C
DVDD = 2.7 V to 3.6 V V min V max A max pF max V min V max A max V min pF typ ns max
Total for all pins; TA = TMIN to TMAX
SMBus-compatible at DVDD < 3.6 V SMBus-compatible at DVDD < 3.6 V
Input filtering suppresses noise spikes of less than 50 ns
Rev. A | Page 7 of 36
AD5384
Parameter LOGIC OUTPUTS (BUSY, SDO)3 VOL, Output Low Voltage VOH, Output High Voltage High Impedance Leakage Current High Impedance Output Capacitance LOGIC OUTPUT (SDA)3 VOL, Output Low Voltage Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS AVDD DVDD Power Supply Sensitivity3 Midscale/VDD AIDD DIDD AIDD (Power-Down) DIDD (Power-Down) Power Dissipation AD5384-31 0.4 DVDD - 0.5 1 5 0.4 0.6 1 8 2.7/3.6 2.7/3.6 -85 0.375 0.475 1 2 20 48 Unit V max V min A max pF typ V max V max A max pF typ V min/max V min/max dB typ mA/channel max mA/channel max mA max A max A max mW max Test Conditions/Comments Sinking 200 A Sourcing 200 A SDO only SDO only ISINK = 3 mA ISINK = 6 mA
Outputs unloaded, boost off; 0.25 mA/channel typ Outputs unloaded, boost on; 0.325 mA/channel typ VIH = DVDD, VIL = DGND Typically 200 nA Typically 1 A Outputs unloaded, boost off, AVDD = DVDD = 3 V
1 2 3
AD5384-3 is calibrated using an external 1.25 V reference. Temperature range is -40C to +85C. Accuracy guaranteed from VOUT = 10 mV to AVDD - 50 mV. Guaranteed by characterization, not production tested. 4 Default on the AD5384-3 is 1.25 V. Programmable to 2.5 V via CR12 in the AD5384 control register; operating the AD5384-3 with a 2.5 V reference will lead to degraded accuracy specifications and limited input code range.
Rev. A | Page 8 of 36
AD5384
AC CHARACTERISTICS1
AVDD = 2.7 V to 3.6 V and 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V. Table 6.
Parameter DYNAMIC PERFORMANCE Output Voltage Settling Time 8 10 2 3 12 15 100 1 0.8 0.1 15 40 150 100 s typ s max V/s typ V/s typ nV-s typ mV typ dB typ nV-s typ nV-s typ nV-s typ V p-p typ V p-p typ nV/Hz typ nV/Hz typ AD5384-3 Unit Test Conditions/Comments Boost mode off, CR11 = 0 1/4 scale to 3/4 scale change settling to 1 LSB
Slew Rate2 Digital-to-Analog Glitch Energy Glitch Impulse Peak Amplitude Channel-to-Channel Isolation DAC-to-DAC Crosstalk Digital Crosstalk Digital Feedthrough Output Noise 0.1 Hz to 10 Hz Output Noise Spectral Density @ 1 kHz @ 10 kHz
Boost mode off, CR11 = 0 Boost mode on, CR11 = 1
See the Terminology section See the Terminology section Effect of input bus activity on DAC output under test External reference, midscale loaded to DAC Internal reference, midscale loaded to DAC
1 2
Guaranteed by design and characterization, not production tested. The slew rate can be programmed via the current boost control bit (CR11 ) in the AD5384 control register.
Rev. A | Page 9 of 36
AD5384 TIMING CHARACTERISTICS
SERIAL INTERFACE
DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications TMIN to TMAX, unless otherwise noted. Table 7.
Parameter1, 2, 3 t1 t2 t3 t4 t5 4 t64 t7 t7A t8 t9 t104 t11 t124 t13 t14 t15 t16 t17 t18 t19 t20 5 t215 t225 t23 Limit at TMIN, TMAX 33 13 13 13 13 33 10 50 5 4.5 30 670 20 20 100 0 100 8 20 12 20 5 8 20 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns max ns max ns min ns min ns max ns min ns min s typ ns min s max ns max ns min ns min ns min Description SCLK cycle time SCLK high time SCLK low time SYNC falling edge to SCLK falling edge setup time 24th SCLK falling edge to SYNC falling edge Minimum SYNC low time Minimum SYNC high time Minimum SYNC high time in readback mode Data setup time Data hold time 24th SCLK falling edge to BUSY falling edge BUSY pulse width low (single channel update) 24th SCLK falling edge to LDAC falling edge LDAC pulse width low BUSY rising edge to DAC output response time BUSY rising edge to LDAC falling edge LDAC falling edge to DAC output response time DAC output settling time boost mode off CLR pulse width low CLR pulse activation time SCLK rising edge to SDO valid SCLK falling edge to SYNC rising edge SYNC rising edge to SCLK rising edge SYNC rising edge to LDAC falling edge
1 2 3
Guaranteed by design and characterization, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD), and are timed from a voltage level of 1.2 V. See Figure 2, Figure 3, Figure 5, and Figure 6. 4 Standalone mode only. 5 Daisy-chain mode only.
200A
IOL
TO OUTPUT PIN CL 50pF 200A IOH
VOH (MIN) OR VOL (MAX)
04652-0-003
Figure 2. Load Circuit for Digital Output Timing
Rev. A | Page 10 of 36
AD5384
t1
SCLK 1 2 24 24
t4
SYNC
t3 t6 t8 t9
t2
t5
t7
DIN DB23
DB0
t10
BUSY
t11 t13 t17 t14 t15 t13 t17
t12
LDAC1 VOUT1
LDAC2
t16
VOUT2
t18
CLR
t19
1LDAC ACTIVE DURING BUSY 2LDAC ACTIVE AFTER BUSY
04652-0-004
VOUT
Figure 3. Serial Interface Timing Diagram (Standalone Mode)
SCLK
24
48
t7A
SYNC
DIN
DB23
DB0
DB23
DB0
INPUT WORD SPECIFIES REGISTER TO BE READ SDO UNDEFINED DB23
NOP CONDITION
DB0
03731-0-005
SELECTED REGISTER DATA CLOCKED OUT
Figure 4. Serial Interface Timing Diagram (Data Readback Mode)
t1
SCLK 24 48
t7
SYNC
t3 t4 t8 t9
t2
t22 t21
DIN
DB23
DB0
DB23
DB0
INPUT WORD FOR DAC N
INPUT WORD FOR DAC N + 1
t20
SDO DB23 DB0
UNDEFINED
INPUT WORD FOR DAC N
t13 t23
04652-0-005
LDAC
Figure 5. Serial Interface Timing Diagram (Daisy-Chain Mode)
Rev. A | Page 11 of 36
AD5384
I2C SERIAL INTERFACE
DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications TMIN to TMAX, unless otherwise noted. Table 8.
Parameter1 FSCL t1 t2 t3 t4 t5 t62 t7 t8 t9 t10 t11 Limit at TMIN, TMAX 400 2.5 0.6 1.3 0.6 100 0.9 0 0.6 0.6 1.3 300 0 300 0 300 20 + 0.1Cb 3 400 Unit kHz max s min s min s min s min ns min s max s min s min s m0in s min ns max ns min ns max ns min ns max ns min pF max Description SCL clock frequency SCL cycle time tHIGH, SCL high time tLOW, SCL low time tHD,STA, start/repeated start condition hold time tSU,DAT, data setup time tHD,DAT, data hold time tHD,DAT, data hold time tSU,STA, setup time for repeated start tSU,STO, stop condition setup time tBUF, bus free time between a STOP and a START condition tR, rise time of SCL and SDA when receiving tR, rise time of SCL and SDA when receiving (CMOS-compatible) tF, fall time of SDA when transmitting tF, fall time of SDA when receiving (CMOS-compatible) tF, fall time of SCL and SDA when receiving tF, fall time of SCL and SDA when transmitting Capacitive load for each bus line
Cb
1 2
See Figure 6. A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) in order to bridge the undefined region of SCL's falling edge. 3 Cb is the total capacitance, in pF, of one bus line. tR and tF are measured between 0.3 DVDD and 0.7 DVDD.
SDA
t9
t3
t10
t11
t4
SCL
t4
START CONDITION
t6
t2
t5 t7
REPEATED START CONDITION
t1
t8
STOP CONDITION
04652-0-006
Figure 6. I 2C-Compatible Serial Interface Timing Diagram
Rev. A | Page 12 of 36
AD5384 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted.1 Table 9.
Parameter AVDD to AGND DVDD to DGND Digital Inputs to DGND SDA/SCL to DGND Digital Outputs to DGND REFIN/REFOUT to AGND AGND to DGND VOUTx to AGND Analog Inputs to AGND Operating Temperature Range Commercial (B Version) Storage Temperature Range JunctionTemperature (TJ max) 100-lead CSPBGA Package JAThermal Impedance Reflow Soldering Peak Temperature Rating -0.3 V to +7 V -0.3 V to +7 V -0.3 V to DVDD + 0.3 V -0.3 V to + 7 V -0.3 V to DVDD + 0.3 V -0.3 V to AVDD + 0.3 V -0.3 V to +0.3 V -0.3 V to AVDD + 0.3 V -0.3 V to AVDD + 0.3 V -40C to +85C -65C to +150C 150C 40C/W 230C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
1
Transient currents of up to 100 mA do not cause SCR latch-up.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 13 of 36
AD5384 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1 2 3 4 5 6 7 8 9 10 11 12
A B C D E F G H J K L M TOP VIEW
A B C D E F G H J K L M
04652-0-007
1
2
3
4
5
6
7
8
9
10 11 12
Figure 7. 100-Lead CSPBGA Pin Configuration
Table 10. Pin Number and Name
CSPBGA Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 Ball Name NC VOUT24 CLR SYNC SCLK DVDD1 DGND PD DCEN LDAC BUSY NC VOUT25 NC DGND DIN SDO DVDD3 DGND SPI/I2C CSPBGA Number B9 B10 B11 B12 C1 C2 C11 C12 D1 D2 D4 D5 D6 D7 D8 D9 D11 D12 E1 E2 Ball Name RESET VOUT22 NC VOUT23 VOUT26 SIGNAL GND4 NC VOUT21 VOUT27 SIGNAL GND4 DACGND4 AGND4 DVDD2 DGND AGND3 DACGND3 VOUT20 AVDD3 AVDD4 SIGNAL GND1 CSPBGA Number E4 E9 E11 E12 F1 F2 F4 F9 F11 F12 G1 G2 G4 G9 G11 G12 H1 H2 H4 H9 Ball Name DACGND4 DACGND3 VOUT17 VOUT19 REFGND SIGNAL GND1 DACGND1 SIGNAL GND3 VOUT16 VOUT18 VOUT28 VOUT29 DACGND1 SIGNAL GND3 VOUT15 AVDD2 REFOUT/REFIN VOUT31 DACGND5 SIGNAL GND2 CSPBGA Number H11 H12 J1 J2 J4 J5 J6 J7 J8 J9 J11 J12 K1 K2 K11 K12 L1 L2 L3 L4 Ball Name VOUT13 VOUT14 AVDD1 VOUT30 DACGND5 AGND1 DACGND2 DACGND2 AGND2 SIGNAL GND2 VOUT12 VOUT11 VOUT0 VOUT1 NC VOUT10 VOUT2 NC SIGNAL GND5 SIGNAL GND5 CSPBGA Number L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 Ball Name AGND5 VOUT6 VOUT32 VOUT34 VOUT36 VOUT38 NC VOUT9 NC VOUT3 VOUT4 VOUT5 AVDD5 VOUT7 VOUT33 VOUT35 VOUT37 VOUT39/ MON_OUT VOUT8 NC
Rev. A | Page 14 of 36
AD5384
Table 11. Pin Function Descriptions
Mnemonic VOUTx SIGNAL GND(1-5) DAC GND(1-5) AGND(1-5) AVDD(1-5) Function Buffered Analog Outputs for Channel x. Each analog output is driven by a rail-to-rail output amplifier operating at a gain of 2. Each output is capable of driving an output load of 5 k to ground. Typical output impedance is 0.5 . Analog Ground Reference Points for Each Group of Eight Output Channels. All SIGNAL_GND pins are tied together internally and should be connected to the AGND plane as close as possible to the AD5384. Each group of eight channels contains a DAC_GND pin. This is the ground reference point for the internal 14-bit DAC. These pins shound be connected to the AGND plane. Analog Ground Reference Point. Each group of eight channels contains an AGND pin. All AGND pins should be connected externally to the AGND plane. Analog Supply Pins. Each group of eight channels has a separate AVDD pin. These pins are shorted internally and should be decoupled with a 0.1 F ceramic capacitor and a 10 F tantalum capacitor. Operating range for the AD5384-5 is 4.5 V to 5.5 V; operating range for the AD5384-3 is 2.7 V to 3.6 V. Ground for All Digital Circuitry. Logic Power Supply. Guaranteed operating range is 2.7 V to 5.5 V. It is recommended that these pins be decoupled with 0.1 F ceramic and 10 F tantalum capacitors to DGND. Ground Reference Point for the Internal Reference. The AD5384 contains a common REFOUT/REFIN pin. The default for this pin is a reference input. When the internal reference is selected, this pin is the reference output. If the application requires an external reference, it can be applied to this pin. The internal reference is enabled/disabled via the control register. This pin has a dual function. It acts a a buffered output for Channel 39 in default mode. But when the monitor function is enabled, this pin acts as the output of a 39-to-1 channel multiplexer that can be programmed to multiplex one of Channels 0 to 38 to the MON_OUT pin. The MON_OUT pin output impedance typically is 500 and is intended to drive a high input impedance like that exhibited by SAR ADC inputs. Serial Interface Mode. This is the frame synchronization input signal for the serial clocks before the addressed register is updated. I2C Mode. This pin acts as a hardware address pin used in conjunction with AD1 to determine the software address for the device on the I2C bus. Multifunction Pin. In serial interface mode, this pin acts as a daisy-chain enable in SPI mode and as a hardware address pin in I2C mode. Serial Interface. Daisy-chain select input (level sensitive, active high). When high, this signal is used in conjunction with SPI/ I2C high to enable the SPI serial interface daisy-chain mode. I2C Mode. This pin acts as a hardware address pin used in conjunction with AD0 to determine the software address for this device on the I2C bus. Serial Data Output in Serial Interface Mode. Three-stateable CMOS output. SDO can be used for daisy-chaining a number of devices together. Data is clocked out on SDO on the rising edge of SCLK, and is valid on the falling edge of SCLK. Digital CMOS Output. BUSY goes low during internal calculations of the data (x2) loaded to the DAC data register. During this time, the user can continue writing new data to the x1, c, and m registers, but no further updates to the DAC registers and DAC outputs can take place. If LDAC is taken low while BUSY is low, this event is stored. BUSY also goes low during power-on reset, and when the BUSY pin is low. During this time, the interface is disabled and any events on LDAC are ignored. A CLR operation also brings BUSY low. Load DAC Logic Input (Active Low). If LDAC is taken low while BUSY is inactive (high), the contents of the input registers are transferred to the DAC registers, and the DAC outputs are updated. If LDAC is taken low while BUSY is active and internal calculations are taking place, the LDAC event is stored and the DAC registers are updated when BUSY goes inactive. However, any events on LDAC during power-on reset or on RESET are ignored. Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is activated, all channels are updated with the data in the CLR code register. BUSY is low for a duration of 35 s while all channels are being updated with the CLR code. Asynchronous Digital Reset Input (Falling Edge Sensitive). The function of this pin is equivalent to that of the poweron reset generator. When this pin is taken low, the state machine initiates a reset sequence to digitally reset the x1, m, c, and x2 registers to their default power-on values. This sequence typically takes 270 s. The falling edge of RESET initiates the RESET process and BUSY goes low for the duration, returning high when RESET is complete. While BUSY is low, all interfaces are disabled and all LDAC pulses are ignored. When BUSY returns high, the part resumes normal operation and the status of the RESET pin is ignored until the next falling edge is detected.
DGND DVDD REF GND REFOUT/REFIN
VOUT39/MON_OUT
SYNC/AD0
DCEN/ AD1
SDO
LDAC
CLR
RESET
Rev. A | Page 15 of 36
AD5384
Mnemonic PD Function Power Down (Level Sensitive, Active High). PD is used to place the device in low power mode, where AIDD reduces to 2 A and DIDD to 20 A. In power-down mode, all internal analog circuitry is placed in low power mode, and the analog output is configured as a high impedance output or provides a 100 k load to ground, depending on how the power-down mode is configured. The serial interface remains active during power-down. No Connect. The user is advised not to connect any signals to these pins. This pin acts as serial interface mode select. When this input is high SPI mode is selected. When low, I2C is selected. Serial Interface Mode. In serial interface mode, data is clocked into the shift register on the falling edge of SCLK. This operates at clock speeds up to 30 MHz. I2C Mode. In I2C mode, this pin performs the SCL function, clocking data into the device. The data transfer rate in I2C mode is compatible with both 100 kHz and 400 kHz operating modes. Serial Interface Mode. In serial interface mode, this pin acts as the serial data input. Data must be valid on the falling edge of SCLK. I2C Mode. In I2C mode, this pin is the serial data pin (SDA) operating as an open-drain input/output.
NC SPI/ I2C SCLK/SCL
DIN/SDA
Rev. A | Page 16 of 36
AD5384 TERMINOLOGY
Relative Accuracy Relative accuracy or endpoint linearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero-scale error and full-scale error, and is expressed in LSB. Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. Zero-Scale Error Zero-scale error is the error in the DAC output voltage when all 0s are loaded into the DAC register. Ideally, with all 0s loaded to the DAC and m = all 1s, c = 2n - 1 VOUT(Zero-Scale) = 0 V Zero-scale error is a measure of the difference between VOUT (actual) and VOUT (ideal), expressed in mV. It is mainly due to offsets in the output amplifier. Offset Error Offset error is a measure of the difference between VOUT (actual) and VOUT (ideal) in the linear region of the transfer function, expressed in mV. Offset error is measured on the AD5384-5 with Code 32 loaded into the DAC register, and on the AD5384-3 with Code 64. Gain Error Gain Error is specified in the linear region of the output range between VOUT = 10 mV and VOUT = AVDD - 50 mV. It is the deviation in slope of the DAC transfer characteristic from the ideal and is expressed in %FSR with the DAC output unloaded. DC Crosstalk This is the dc change in the output level of one DAC at midscale in response to a full-scale code (all 0s to all 1s, and vice versa) and output change of all other DACs. It is expressed in LSB. Digital crosstalk is the glitch impulse transferred to the output of one converter due to a change in the DAC register code of another converter. It is specified is specified in nV-s. Digital Feedthrough When the device is not selected, high frequency logic activity on the device's digital inputs can be capacitively coupled both across and through the device to show up as noise on the VOUT pins. It can also be coupled along the supply and ground lines. This noise is digital feedthrough. Output Noise Spectral Density This is a measure of internally generated random noise. Random noise is characterized as a spectral density (voltage per Hertz). It is measured by loading all DACs to midscale and measuring noise at the output. It is measured in nV/Hz in a 1 Hz bandwidth at 10 kHz. DC Output Impedance This is the effective output source resistance. It is dominated by package lead resistance. Output Voltage Settling Time This is the amount of time it takes for the output of a DAC to settle to a specified level for a 1/4 to 3/4 full-scale input change, and is measured from the BUSY rising edge. Digital-to-Analog Glitch Energy This is the amount of energy injected into the analog output at the major code transition. It is specified as the area of the glitch in nV-s. It is measured by toggling the DAC register data between 0x1FFF and 0x2000. DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse that appears at the output of one DAC due to both the digital change and the subsequent analog output change at another DAC. The victim channel is loaded with midscale. DAC-to-DAC crosstalk is specified in nV-s. Digital Crosstalk
Rev. A | Page 17 of 36
AD5384 TYPICAL PERFORMANCE CHARACTERISTICS
2.0 1.5 1.0
INL ERROR (LSB)
AVDD = DVDD = 5.5V VREF = 2.5V TA = 25C
2.0 1.5 1.0
INL ERROR (LSB)
AVDD = DVDD = 3V VREF = 1.25V TA = 25C
0.5 0 -0.5 -1.0 -1.5
03731-0-033
0.5 0 -0.5 -1.0 -1.5 -2.0 0 4096 8192 INPUT CODE 12288 16384
03731-0-035
03731-0-048
-2.0 0 4096 8192 INPUT CODE 12288 16384
Figure 8. Typical AD5384-5 INL Plot
Figure 11. Typical AD5384-3 INL Plot
03731-0-034
2.539 2.538 2.537 2.536 2.535 2.534 2.533 2.532 2.531 2.530 2.529 2.528 2.527 2.526 2.525 2.524 2.523 0 50 100 150
AVDD = DVDD = 5V VREF = 2.5V TA = 25C 14ns/SAMPLE NUMBER 1 LSB CHANGE AROUND MIDSCALE GLITCH IMPULSE = 10nV-s
FREQUENCY
40 35 30 25 20 15 10 5 0 -5.0 -4.0 -3.0 -2.0 -1.0 0 1.0 2.0 3.0 4.0 5.0 -4.5 -3.5 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 REFERENCE DRIFT (ppm/C)
AMPLITUDE (V)
200 250 300 350 SAMPLE NUMBER
400
450
500
550
Figure 9. AD5384-5 Glitch Impulse
Figure 12. AD5384-REFOUT Temperature Coefficient
AVDD = DVDD = 5V VREF = 2.5V TA = 25C
VOUT
AVDD = DVDD = 5V VREF = 2.5V TA = 25C
VOUT
03731-0-012
Figure 10. Slew Rate with Boost Off
Figure 13. Slew Rate with Boost On
Rev. A | Page 18 of 36
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AD5384
14 12 AVDD = 5.5V VREF = 2.5V TA = 25C
AVDD = DVDD = 5V VREF = 2.5V TA = 25C POWER SUPPLY RAMP RATE = 10ms VOUT
PERCENTAGE OF UNITS (%)
10 8 6 4 2
04598-0-049
AVDD
8
9
10 AIDD (mA)
11
Figure 14. Histogram with Boost Off
Figure 17. AD5384 Power-Up Transient
10
DVDD = 5.5V VIH = DVDD VIL = DGND TA = 25C
14 12 10 8 6 4 2
04598-0-050
AVDD = 5.5V REFIN = 2.5V TA = 25C
8
NUMBER OF UNITS
6
4
2
NUMBER OF UNITS
03731-0-011
0 0.4 0.5 0.6 0.7 DIDD (mA) 0.8 0.9
0 -2 -1 0 1 INL ERROR DISTRIBUTION (LSB) 2
Figure 15. DIDD Histogram
Figure 18. INL Distribution
WR BUSY
PD
AVDD = DVDD = 5V VREF = 2.5V TA = 25C EXITS SOFT PD TO MIDSCALE
VOUT
VOUT
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AVDD = DVDD = 5V VREF = 2.5V TA = 25C EXITS HARDWARE PD TO MIDSCALE
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Figure 16. Exiting Soft Power Down
Figure 19. Exiting Hardware Power Down
Rev. A | Page 19 of 36
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AD5384
6 FULL-SCALE 5 3/4 SCALE 4 3 2 1 ZERO-SCALE 0
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6 5
AVDD = DVDD = 3V VREF = 1.25V TA = 25C
AVDD = DVDD = 5V VREF = 2.5V TA = 25C
4 3/4 SCALE 3 2 1 0 -1 -40
04652-0-031 04652-0-032
VOUT (V)
1/4 SCALE
VOUT (V)
MIDSCALE
MIDSCALE
FULL-SCALE
ZERO-SCALE -20 -10 -5
1/4 SCALE -2 0 2 CURRENT (mA) 5 10 20 -40
-1 -40
-20
-10
-5
-2 0 2 CURRENT (mA)
5
10
20
40
Figure 20. AD5384-5 Output Amplifier Source and Sink Capability
Figure 23. AD5384-3 Output Amplifier Source and Sink Capability
0.20 0.15 0.10
AVDD = 5V VREF = 2.5V TA = 25C
2.456 2.455 2.454
AMPLITUDE (V)
AVDD = DVDD = 5V VREF = 2.5V TA = 25C 14ns/SAMPLE NUMBER
ERROR VOLTAGE (V)
ERROR AT ZERO SINKING CURRENT 0.05 0 -0.05 -0.10 -0.15 -0.20 0 0.25 0.50 0.75 1.00 1.25 ISOURCE/ISINK (mA) 1.50 1.75 2.00
04652-0-040
2.453 2.452 2.451 2.450 2.449 0 50 100 150 200 250 300 350 SAMPLE NUMBER 400 450 500 550
(VDD-VOUT) AT FULL-SCALE SOURCING CURRENT
Figure 21. Headroom at Rail vs. Source/Sink Current
Figure 24. Adjacent Channel DAC to DAC Crosstalk
600
500
AVDD = 5V TA = 25C REFOUT DECOUPLED WITH 100nF CAPACITOR
OUTPUT NOISE (nV/ Hz)
AVDD = DVDD = 5V TA = 25C DAC LOADED WITH MIDSCALE EXTERNAL REFERENCE Y AXIS = 5V/DIV X AXIS = 100ms/DIV
400
300 REFOUT = 2.5V
200 REFOUT = 1.25V
0 100
1k FREQUENCY (Hz)
10k
100k
Figure 22. REFOUT Noise Spectral Density
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Figure 25. 0.1 Hz to 10 Hz Noise Plot
Rev. A | Page 20 of 36
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100
AVDD = DVDD = 5V VREF = 2.5V TA = 25C EXITS SOFT PD TO MIDSCALE
AD5384 FUNCTIONAL DESCRIPTION
DAC ARCHITECTURE--GENERAL
The AD5384 is a complete single-supply, 40-channel, voltage output DAC offering 14-bit resolution, available in a 100-lead CSPBGA package. It features two serial interfaces, SPI and I2C. This family includes an internal1.25/2.5 V, 10 ppm/C reference that can be used to drive the buffered reference inputs. Alternatively, an external reference can be used to drive these inputs. Reference selection is via a bit in the control register. Internal/external reference selection is via the CR10 bit in the control register; CR12 selects the reference magnitude if the internal reference is selected. All channels have an on-chip output amplifier with rail-to-rail output capable of driving 5 k in parallel with a 200 pF load.
VREF (+) AVDD
The complete transfer function for these devices can be represented as VOUT = 2 x VREF x x2/2n where: x2 is the data-word loaded to the resistor string DAC. VREF is the internal reference voltage or the reference voltage externally applied to the DAC REFOUT/REFIN pin. For specified performance, an external reference voltage of 2.5 V is recommended for the AD5384-5, and 1.25 V for the AD5384-3.
DATA DECODING
The AD5384 contains a 14-bit data bus, DB13-DB0. Depending on the value of REG1 and REG0 outlined in Table 12, this data is loaded into the addressed DAC input register(s), offset (c) register(s), or gain (m) register(s). The format data, offset (c) and gain (m) register contents are outlined in Table 13, Table 14, and Table 15. Table 12. Register Selection
REG1 1 1 0 0 REG0 1 0 1 0 Register Selected Input Data Register (x1) Offset Register (c) Gain Register (m) Special Function Registers (SFRs)
x1 INPUT REG INPUT DATA m REG c REG x2 14-BIT DAC R
04652-0-014
VOUT
R AGND
Figure 26. Single-Channel Architecture
The architecture of a single DAC channel consists of a14-bit resistor-string DAC followed by an output buffer amplifier operating at a gain of 2. This resistor-string architecture guarantees DAC monotonicity. The 14-bitbinary digital code loaded to the DAC register determines at which node on the string the voltage is tapped off before being fed to the output amplifier. Each channel on these devices contains independent offset and gain control registers allowing the user to digitally trim offset and gain. These registers let the user calibrate out errors in the complete signal chain including the DAC using the internal m and c registers which hold the correction factors. All channels are double buffered allowing synchronous updating of all channels using the LDAC pin. Figure 26 shows a block diagram of a single channel on the AD5384. The digital input transfer function for each DAC can be represented as x2 = [(m + 2)/ 2n x x1] + (c - 2n - 1) where: x2 is the data-word loaded to the resistor string DAC. x1 is the 14-bit data-word written to the DAC input register. m is the gain coefficient (default is 0x3FFE on the AD5384). The gain coefficient is written to the 13 most significant bits (DB13 to DB1) and the LSB (DB0) is 0. n is the DAC resolution (n = 14 for AD5384). c is the14-bit offset coefficient (default is 0x2000).
Table 13. DAC Data Format (REG1 = 1, REG0 = 1)
DB13 to DB0 11 1111 11 1111 10 0000 10 0000 01 1111 00 0000 00 0000 1111 1111 0000 0000 1111 0000 0000 1111 1110 0001 0000 1111 0001 0000 DAC Output (V) 2 VREF x (16383/16384) 2 VREF x (16382/16384) 2 VREF x (8193/16384) 2 VREF x (8192/16384) 2 VREF x (8191/16384) 2 VREF x (1/16384) 0
Table 14. Offset Data Format (REG1 = 1, REG0 = 0)
DB13 to DB0 11 1111 11 1111 10 0000 10 0000 01 1111 00 0000 00 0000 1111 1111 0000 0000 1111 0000 0000 1111 1110 0001 0000 1111 0001 0000 Offset (LSB) +8191 +8190 +1 0 -1 -8191 -8192
Rev. A | Page 21 of 36
AD5384
Table 15. Gain Data Format (REG1 = 0, REG0 = 1)
DB13 to DB0 11 1111 10 1111 01 1111 00 1111 00 0000 1111 1111 1111 1111 0000 1110 1110 1110 1110 0000 Gain Factor 1 0.75 0.5 0.25 0
Soft CLR REG1 = REG0 = 0, A5-A0 = 000010 DB13-DB0 = Don't Care Executing this instruction performs the CLR, which is functionally the same as that provided by the external CLR pin. The DAC outputs are loaded with the data in the CLR code register. It takes 35 s to fully execute the SOFT CLR, as indicated by the BUSY low time. Soft Power-Down REG1 = REG0 = 0, A5-A0 = 001000 DB13-DB0 = Don't Care Executing this instruction performs a global power-down that puts all channels into a low power mode that reduces the analog supply current to 2 A maximum and the digital current to 20 A maximum. In power-down mode, the output amplifier can be configured as a high impedance output or can provide a 100 k load to ground. The contents of all internal registers are retained in power-down mode. No register can be written to while in power-down. Soft Power-Up REG1 = REG0 = 0, A5-A0 = 001001 DB13-DB0 = Don't Care This instruction is used to power up the output amplifiers and the internal reference. The time to exit power-down is 8 s. The hardware power-down and software function are internally combined in a digital OR function. Soft RESET REG1 = REG0 = 0, A5-A0 = 001111 DB13-DB0 = Don't Care This instruction is used to implement a software reset. All internal registers are reset to their default values, which correspond to m at full scale and c at zero. The contents of the DAC registers are cleared, setting all analog outputs to 0 V. The soft reset activation time is 135 s.
ON-CHIP SPECIAL FUNCTION REGISTERS (SFR)
The AD5384 contains a number of special function registers (SFRs), as outlined in Table 16. SFRs are addressed with REG1 = REG0 = 0 and are decoded using Address Bits A5 to A0. Table 16. SFR Register Functions (REG1 = 0, REG0 = 0)
R/W X 0 0 0 0 0 1 0 0 A5 0 0 0 0 0 0 0 0 0 A4 0 0 0 0 0 0 0 0 0 A3 0 0 0 1 1 1 1 1 1 A2 0 0 0 0 0 1 1 0 1 A1 0 0 1 0 0 0 0 1 1 A0 0 1 0 0 1 0 0 0 1 Function NOP (No Operation) Write CLR Code Soft CLR Soft Power-Down Soft Power-Up Control Register Write Control Register Read Monitor Channel Soft Reset
SFR COMMANDS
NOP (No Operation) REG1 = REG0 = 0, A5-A0 = 000000 Performs no operation but is useful in serial readback mode to clock out data on DOUT for diagnostic purposes. BUSY pulses low during a NOP operation. Write CLR Code REG1 = REG0 = 0, A5-A0 = 000001 DB13-DB0 = Contain the CLR data Bringing the CLR line low or exercising the soft clear function loads the contents of the DAC registers with the data contained in the user-configurable CLR register, and sets VOUT0 to VOUT39, accordingly. This can be very useful for setting up a specific output voltage in a clear condition. It is also beneficial for calibration purposes; the user can load full scale or zero scale to the clear code register and then issue a hardware or software clear to load this code to all DACs, removing the need for individual writes to each DAC. Default on power-up is all 0s.
Rev. A | Page 22 of 36
AD5384
Table 17. Control Register Contents
MSB CR13 CR12 CR11 CR10 CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 CR1 LSB CR0
Control Register Write/Read REG1 = REG0 = 0, A5-A0 = 001100, R/W status determines if the operation is a write (R/W = 0) or a read (R/W = 1). DB13 to DB0 contain the control register data. Control Register Contents CR13: Power-Down Status. This bit is used to configure the output amplifier state in power-down. CR13 = 1: Amplifier output is high impedance (default on power-up). CR13 = 0: Amplifier output is 100 k to ground. CR12: REF Select. This bit selects the operating internal reference for the AD5384. CR12 is programmed as follows: CR12 = 1: Internal reference is 2.5 V (AD5384-5 default), the recommended operating reference for AD5384-5. CR12 = 0: Internal reference is 1.25 V (AD5384-3 default), the recommended operating reference for AD5384-3. CR11: Current Boost Control. This bit is used to boost the current in the output amplifier, thereby altering its slew rate. This bit is configured as follows: CR11 = 1: Boost Mode On. This maximizes the bias current in the output amplifier, optimizing its slew rate but increasing the power dissipation. CR11 = 0: Boost Mode Off (default on power-up). This reduces the bias current in the output amplifier and reduces the overall power consumption. CR10: Internal/External Reference. This bit determines if the DAC uses its internal reference or an externally applied reference. CR10 = 1: Internal Reference Enabled. The reference output depends on data loaded to CR12. CR10 = 0: External Reference Selected (default on power-up). CR9: Channel Monitor Enable (see Channel Monitor Function). CR9 = 1: Monitor Enabled. This enables the channel monitor function. After a write to the monitor channel in the SFR register, the selected channel output is routed to the MON_OUT pin. VOUT39 operates as the MON_OUT pin. CR9 = 0: Monitor Disabled (default on power-up). When the monitor is disabled, the MON_OUT pin assumes its normal DAC output function. CR8: Thermal Monitor Function. This function is used to monitor the AD5384 internal die temperature, when enabled. The thermal monitor powers down the output amplifiers when the temperature exceeds 130C. This function can be used to protect the device when power dissipation might be exceeded if a number of output channels are simultaneously short-circuited. A soft power-up re-enables the output amplifiers if the die temperature drops below 130C. CR8 = 1: Thermal Monitor Enabled. CR8 = 0: Thermal Monitor Disabled (default on power-up). CR7: Don't Care. CR6 to CR2: Toggle Function Enable. This function allows the user to toggle the output between two codes loaded to the A and B register for each DAC. Control register bits CR6 to CR2 are used to enable individual groups of eight channels for operation in toggle mode. A Logic 1 written to any bit enables a group of channels; a Logic 0 disables a group. LDAC is used to toggle between the two registers. Table 18 shows the decoding for toggle mode operation. For example, CR6 controls group w, which contains Channels 32 to 39, CR6 = 1 enables these channels. CR1 and CR0: Don't Care. Table 18.
CR Bit CR6 CR5 CR4 CR3 CR2 Group 4 3 2 1 0 Channels 32-39 24-31 16-23 8-15 0-7
Channel Monitor Function REG1 = REG0 = 0, A5-A0 = 001010 DB13-DB8 = Contain data to address the monitored channel. A channel monitor function is provided on the AD5384. This feature, which consists of a multiplexer addressed via the interface, allows any channel output to be routed to the MON_OUT pin for monitoring using an external ADC. In channel monitor mode, VOUT39 becomes the MON_OUT pin, to which all monitored pins are routed. The channel monitor function must be enabled in the control register before any channels are routed to MON_OUT. On the AD5384, DB13 to DB8 contain the channel address for the monitored channel. Selecting Channel Address 63 three-states MON_OUT.
Rev. A | Page 23 of 36
AD5384
Table 19. AD5384 Channel Monitor Decoding
REG1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * 0 0 REG0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * 0 0 A5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * 0 0 A4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * 0 0 A3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 * 1 1 A2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * 0 0 A1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 * 1 1 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * 0 0 DB13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 * 1 1 DB12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 * 1 1 DB11 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 1 * 1 1 DB10 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 * 1 1 DB9 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 * 1 1 DB8 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 * 0 1 DB7-DB0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X * X X MON_OUT VOUT0 VOUT1 VOUT2 VOUT3 VOUT4 VOUT5 VOUT6 VOUT7 VOUT8 VOUT9 VOUT10 VOUT11 VOUT12 VOUT13 VOUT14 VOUT15 VOUT16 VOUT17 VOUT18 VOUT19 VOUT20 VOUT21 VOUT22 VOUT23 VOUT24 VOUT25 VOUT26 VOUT27 VOUT28 VOUT29 VOUT30 VOUT31 VOUT32 VOUT33 VOUT34 VOUT35 VOUT36 VOUT37 VOUT38 VOUT39 Undefined * Undefined Three-State
REG1 REG0 A5 A4 A3 A2 A1 A0
0 VOUT0 VOUT1
0
0
0
1
0
1
0
AD5384 CHANNEL MONITOR DECODING VOUT37 VOUT38 CHANNEL ADDRESS DB13-DB8
VOUT39/MON_OUT
Figure 27. Channel Monitor Decoding
Rev. A | Page 24 of 36
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AD5384 HARDWARE FUNCTIONS
RESET FUNCTION
Bringing the RESET line low resets the contents of all internal registers to their power-on reset state. Reset is a negative edgesensitive input. The default corresponds to m at full scale and to c at zero. The contents of the DAC registers are cleared, setting VOUT0 to VOUT39 to 0 V. The hardware reset activation time takes 270 s. The falling edge of RESET initiates the reset process; BUSY goes low for the duration, returning high when RESET is complete. While BUSY is low, all interfaces are disabled and all LDAC pulses are ignored. When BUSY returns high, the part resumes normal operation and the status of the RESET pin is ignored until the next falling edge is detected. outputs update immediately after BUSY goes high. BUSY also goes low during power-on reset and when a falling edge is detected on the RESET pin. During this time, all interfaces are disabled and any events on LDAC are ignored. The AD5384 contains an extra feature whereby a DAC register is not updated unless its x2 register has been written to since the last time LDAC was brought low. Normally, when LDAC is brought low, the DAC registers are filled with the contents of the x2 registers. However, the AD5384 updates the DAC register only if the x2 data has changed, thereby removing unnecessary digital crosstalk.
POWER-ON RESET
The AD5384 contains a power-on reset generator and state machine. The power-on reset resets all registers to a predefined state and configures the analog outputs as high impedance. The BUSY pin goes low during the power-on reset sequencing, preventing data writes to the device.
ASYNCHRONOUS CLEAR FUNCTION
Bringing the CLR line low clears the contents of the DAC registers to the data contained in the user configurable CLR register and sets VOUT0 to VOUT39 accordingly. This function can be used in system calibration to load zero scale and full scale to all channels. The execution time for a CLR is 35 s.
POWER-DOWN
The AD5384 contains a global power-down feature that puts all channels into a low power mode and reduces the analog power consumption to 2 A maximum and digital power consumption to 20 A maximum. In power-down mode, the output amplifier can be configured as a high impedance output or it can provide a 100 k load to ground. The contents of all internal registers are retained in power-down mode. When exiting power-down, the settling time of the amplifier elapses before the outputs settles to their correct values.
BUSY AND LDAC FUNCTIONS
BUSY is a digital CMOS output that indicates the status of the AD5384. The value of x2, the internal data loaded to the DAC data register, is calculated each time the user writes new data to the corresponding x1, c ,or m registers. During the calculation of x2, the BUSY output goes low. While BUSY is low, the user can continue writing new data to the x1, m, or c registers, but no DAC output updates can take place. The DAC outputs are updated by taking the LDAC input low. If LDAC goes low while BUSY is active, the LDAC event is stored and the DAC outputs update immediately after BUSY goes high. The user can hold the LDAC input permanently low, in which case the DAC
Rev. A | Page 25 of 36
AD5384 INTERFACES
The AD5384 contains a serial interface that can be programmed either as DSP-, SPI-, MICROWIRE-, or I2Ccompatible. The SPI/I2C pin is used to select DSP, SPI, MICROWIRE, or I2C interface mode. To minimize both the power consumption of the device and the on-chip digital noise, the active interface powers up fully only when the device is being written to, i.e., on the falling edge of SYNC. A/B. When toggle mode is enabled, this selects whether the data write is to the A or B register, with Toggle disabled this bit should be set to zero to select the A data register. R/W is the read or write control bit. A5-A0 are used to address the input channels. REG1 and REG0 select the register to which data is written, as shown in Table 12. DB13-DB0 contain the input data-word. X is a don't care condition. Standalone Mode By connecting DCEN (daisy-chain enable) pin low, standalone mode is enabled. The serial interface works with both a continuous and a noncontinuous serial clock. The first falling edge of SYNC starts the write cycle and resets a counter that counts the number of serial clocks to ensure that the correct number of bits are shifted into the serial shift register. Any further edges on SYNC, except for a falling edge, are ignored until 24 bits are clocked in. Once 24 bits are shifted in, the SCLK is ignored. For another serial transfer to take place, the counter must be reset by the falling edge of SYNC.
DSP-, SPI-, MICROWIRE-COMPATIBLE SERIAL INTERFACES
The serial interface can be operated with a minimum of three wires in standalone mode or five wires in daisy-chain mode. Daisy chaining allows many devices to be cascaded together to increase system channel count. The SPI/I2C (Ball B8) should be tied high to enable the DSP-, SPI-, MICROWIRE-compatible serial interface. The serial interface control pins are SYNC, DIN, SCLK--Standard 3-Wire Interface Pins. DCEN--Selects Standalone Mode or Daisy-Chain Mode. SDO--Data Out Pin for Daisy-Chain Mode. Figure 3 and Figure 5 show the timing diagrams for a serial write to the AD5384 in standalone and in daisy-chain modes. The 24-bit data-word format for the serial interface is shown in Table 20.
Table 20. 40-Channel, 14-Bit DAC Serial Input Register Configuration
MSB A/B R/W A5 A4 A3 A2 A1 A0 REG1 REG0 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 LSB DB0
Rev. A | Page 26 of 36
AD5384
Daisy-Chain Mode For systems that contain several devices, the SDO pin can be used to daisy-chain several devices together. This daisy-chain mode can be useful in system diagnostics and in reducing the number of serial interface lines. By connecting DCEN (daisy-chain enable) pin high, the daisychain mode is enabled. The first falling edge of SYNC starts the write cycle. The SCLK is applied continuously to the input shift register when SYNC is low. If more than 24 clock pulses are applied, the data ripples out of the shift register and appears on the SDO line. This data is clocked out on the rising edge of SCLK and is valid on the falling edge. By connecting the SDO of the first device to the DIN input on the next device in the chain, a multidevice interface is constructed. 24 clock pulses are required for each device in the system. Therefore, the total number of clock cycles must equal 24N where N is the total number of AD5384 devices in the chain. When the serial transfer to all devices is complete, SYNC is taken high. This latches the input data in each device in the daisy-chain and prevents any further data being clocked into the input shift register. If the SYNC is taken high before 24 clocks are clocked into the part, this is considered a bad frame and the data is discarded. The serial clock may be either a continuous or a gated clock. A continuous SCLK source can be used only if it can be arranged that SYNC is held low for the correct number of clock cycles. In gated clock mode a burst clock containing the exact number of clock cycles must be used and SYNC taken high after the final clock to latch the data. Readback Mode Readback mode is invoked by setting the R/W bit = 1 in the serial input register write. With R/W = 1, Bits A5 to A0, in association with Bits REG1 and REG0, select the register to be read. The remaining data bits in the write sequence are don't cares. During the next SPI write, the data appearing on the SDO output contains the data from the previously addressed register. For a read of a single register, the NOP command can be used in clocking out the data from the selected register on SDO. Figure 28 shows the readback sequence. For example, to read back the m register of Channel 0 on the AD5384, the following sequence should be followed. First, write 0x404XXX to the AD5384 input register. This configures the AD5384 for read mode with the m register of Channel 0 selected. Note that Data Bits DB13 to DB0 are don't cares. Follow this with a second write, a NOP condition, 0x000000. During this write, the data from the m register is clocked out on the SDO line, i.e., data clocked out contains the data from the m register in Bits DB13 to DB0, and the top 10 bits contain the address information as previously written. In readback mode, the SYNC signal must frame the data. Data is clocked out on the rising edge of SCLK and is valid on the falling edge of the SCLK signal. If the SCLK idles high between the write and read operations of a readback operation, the first bit of data is clocked out on the falling edge of SYNC.
SCLK
24
48
SYNC
DIN
DB23
DB0
DB23
DB0
INPUT WORD SPECIFIES REGISTER TO BE READ
NOP CONDITION
SDO
DB23
DB0
04652-0-016
UNDEFINED
SELECTED REGISTER DATA CLOCKED OUT
Figure 28. Serial Readback Operation
Rev. A | Page 27 of 36
AD5384
I2C SERIAL INTERFACE
The AD5384 features an I2C-compatible 2-wire interface consisting of a serial data line (SDA) and a serial clock line (SCL). SDA and SCL facilitate communication between the AD5384 and the master at rates up to 400 kHz. Figure 6 shows the 2-wire interface timing diagrams that incorporate three different modes of operation. Select I2C mode by configuring the SPI/I2C pin to a Logic 0. The device is connected to this bus as slave devices, i.e., no clock is generated by the AD5384. The AD5384 has a 7-bit slave address 1010 1(AD1)(AD0). The 5 MSBs are hard coded, and the two LSBs are determined by the state of the AD1 AD0 pins. The ability to hardware-configure AD1 and AD0 allows four of these devices to be configured on the bus. I2C Data Transfer One data bit is transferred during each SCL clock cycle. The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high are control signals, which configure start and stop conditions. Both SDA and SCL are pulled high by the external pull-up resistors when the I2C bus is not busy. Start and Stop Conditions A master device initiates communication by issuing a start condition. A start condition is a high-to-low transition on SDA with SCL high. A stop condition is a low-to-high transition on SDA while SCL is high. A start condition from the master signals the beginning of a transmission to the AD5384. The stop condition frees the bus. If a repeated start condition (Sr) is generated instead of a stop condition, the bus remains active. Repeated START Conditions A repeated start (Sr) condition may indicate a change of data direction on the bus. Sr may be used when the bus master is writing to several I2C devices and wants to maintain control of the bus. Acknowledge Bit (ACK) The acknowledge bit (ACK) is the ninth bit attached to any 8-bit data-word. ACK is always generated by the receiving device. The AD5384 devices generate an ACK when receiving an address or data by pulling SDA low during the ninth clock period. Monitoring ACK allows detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault occurs. In the event of an unsuccessful data transfer, the bus master should re-attempt communication. Slave Addresses A bus master initiates communication with a slave device by issuing a start condition followed by the 7-bit slave address. When idle, the AD5384 waits for a start condition followed by its slave address. The LSB of the address word is the Read/Write (R/W) bit. The AD5384 devices are receive-only devices; when communicating with these, R/W = 0. After receiving the proper address 1010 1(AD1)(AD0), the AD5384 issues an ACK by pulling SDA low for one clock cycle. The AD5384 has four different user programmable addresses determined by the AD1 and AD0 bits. Write Operation There are three specific modes in which data can be written to the AD5384 family of DACs. 4-Byte Mode When writing to the AD5384 DACs, the user must begin with an address byte (R/W = 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. The address byte is followed by the pointer byte; this addresses the specific channel in the DAC to be addressed and also is acknowledged by the DAC. Two bytes of data are then written to the DAC, as shown in Figure 29. A stop condition follows. This lets the user update a single channel within the AD5384 at any time and requires four bytes of data to be transferred from the master. 3-Byte Mode In 3-byte mode, the user can update more than one channel in a write sequence without having to write the device address byte each time. The device address byte is required only once; subsequent channel updates require the pointer byte and the data bytes. In 3-byte mode, the user begins with an address byte (R/W = 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. The address byte is followed by the pointer byte. This addresses the specific channel in the DAC to be addressed and also is acknowledged by the DAC. This is then followed by the two data bytes, REG1 and REG0, which determine the register to be updated. If a stop condition does not follow the data bytes, another channel can be updated by sending a new pointer byte followed by the data bytes. This mode requires only three bytes to be sent to update any channel once the device is initially addressed, and reduces the software overhead in updating the AD5384 channels. A stop condition at any time exits this mode. Figure 30 shows a typical configuration.
Rev. A | Page 28 of 36
AD5384
SCL
SDA
1
0
1
0
1
AD1
AD0
R/W ACK BY AD538x
0 MSB
0
A5
A4
A3
A2
A1
A0 ACK BY AD538x
START COND BY MASTER ADDRESS BYTE
POINTER BYTE
SCL
SDA
REG1
REG0
MSB
LSB ACK BY AD538x
MSB
LSB
04652-0-017 04652-0-018
ACK BY AD538x LEAST SIGNIFICANT BYTE
MOST SIGNIFICANT BYTE
STOP COND BY MASTER
Figure 29. 4-Byte AD5384, I2C Write Operation
SCL
SDA
1
0
1
0
1
AD1
AD0
R/W ACK BY AD538x
0 MSB
0
A5
A4
A3
A2
A1
A0 ACK BY AD538x
START COND BY MASTER ADDRESS BYTE
POINTER BYTE FOR CHANNEL "N"
SCL
SDA
REG1
REG0
MSB
LSB ACK BY AD538x
MSB
LSB ACK BY AD538x LEAST SIGNIFICANT DATA BYTE
MOST SIGNIFICANT DATA BYTE DATA FOR CHANNEL "N" SCL
SDA
0 MSB
0
A5
A4
A3
A2
A1
A0 ACK BY AD538x
POINTER BYTE FOR CHANNEL "NEXT CHANNEL"
SCL
SDA
REG1
REG0
MSB
LSB ACK BY AD538x
MSB
LSB ACK BY AD538x LEAST SIGNIFICANT DATA BYTE STOP COND BY MASTER
MOST SIGNIFICANT DATA BYTE DATA FOR CHANNEL "NEXT CHANNEL"
Figure 30. 3-Byte AD5384, I2C Write Operation
Rev. A | Page 29 of 36
AD5384
2-Byte Mode Following initialization of 2-byte mode, the user can update channels sequentially. The device address byte is required only once, and the pointer address pointer is configured for autoincrement or burst mode. The user must begin with an address byte (R/W = 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. The address byte is followed by a specific pointer byte (0xFF) that initiates the burst mode of operation. The address pointer initializes to Channel 0,and, upon receiving the two data bytes for the present address, automatically increments to the next address. The REG0 and REG1 bits in the data byte determine which register is updated. In this mode, following the initialization, only the two data bytes are required to update a channel. The channel address automatically increments from Address 0. This mode allows transmission of data to all channels in one block and reduces the software overhead in configuring all channels. A stop condition at any time exits this mode. Toggle mode is not supported in 2-byte mode. Figure 31 shows a typical configuration.
SCL
SDA
1
0
1
0
1
AD1
AD0
R/W ACK BY AD538x
0 MSB
0
A5 = 1
A4 = 1 A3 = 1 A2 = 1
A1 = 1 A0 = 1 ACK BY AD538x
START COND BY MASTER ADDRESS BYTE
POINTER BYTE
SCL
SDA
REG1
REG0
MSB
LSB ACK BY AD538x
MSB
LSB ACK BY AD538x LEAST SIGNIFICANT DATA BYTE
MOST SIGNIFICANT DATA BYTE CHANNEL 0 DATA SCL
SDA
REG1
REG0
MSB
LSB ACK BY AD538x
MSB
LSB ACK BY CONVERTER LEAST SIGNIFICANT DATA BYTE
MOST SIGNIFICANT DATA BYTE CHANNEL 1 DATA SCL
SDA
REG1
REG0
MSB
LSB ACK BY AD538x
MSB
LSB ACK BY STOP CONVERTER COND LEAST SIGNIFICANT DATA BYTE BY MASTER
CHANNEL N DATA FOLLOWED BY STOP
Figure 31. 2-Byte, 12C Write Operation
Rev. A | Page 30 of 36
04652-0-019
MOST SIGNIFICANT DATA BYTE
AD5384
MICROPROCESSOR INTERFACING
AD5384 to MC68HC11 The serial peripheral interface (SPI) on the MC68HC11 is configured for master mode (MSTR = 1), the Clock Polarity bit (CPOL) = 0, and the Clock Phase bit (CPHA) = 1. The SPI is configured by writing to the SPI control register (SPCR)--see the 68HC11 User Manual. SCK of the 68HC11 drives the SCLK of the AD5384, the MOSI output drives the serial data line (DIN) of the AD5384, and the MISO input is driven from DOUT. The SYNC signal is derived from a port line (PC7). When data is being transmitted to the AD5384, the SYNC line is taken low (PC7). Data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle.
MC68HC11 DVDD
AD5384 to 8051 The AD5384 requires a clock synchronized to the serial data. The 8051 serial interface must therefore be operated in Mode 0. In this mode, serial data enters and exits through RxD, and a shift clock is output on TxD. Figure 34 shows how the 8051 is connected to the AD5384. Because the AD5384 shifts data out on the rising edge of the shift clock and latches data in on the falling edge, the shift clock must be inverted. The AD5384 requires its data to be MSB first. Since the 8051 outputs the LSB first, the transmit routine must take this into account.
8XC51 DVDD DVDD
AD5384
SPI/I2C RESET
RxD TxD P1.1
SDO DIN SCLK SYNC
04652-0-022
AD5384
SPI/I2C RESET
MISO MOSI SCK PC7
SDO DIN SCLK SYNC
04652-0-020
Figure 34. AD5384-to-8051 Interface
AD5384 to ADSP-2101/ADSP-2103 Figure 35 shows a serial interface between the AD5384 and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should be set up to operate in SPORT transmit alternate framing mode. The ADSP-2101/ADSP-2103 SPORT is programmed through the SPORT control register and should be configured as follows: internal clock operation, active low framing, and 16-bit word length. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled.
ADSP-2101/ ADSP-2103
DVDD
Figure 32. AD5384-toMC68HC11 Interface
AD5384 to PIC16C6x/7x The PIC16C6x/7x synchronous serial port (SSP) is configured as an SPI master with the Clock Polarity bit = 0. This is done by writing to the synchronous serial port control register (SSPCON). See the PIC16/17 Microcontroller User Manual. In this example I/O, port RA1 is being used to pulse SYNC and enable the serial port of the AD5384. This microcontroller transfers only eight bits of data during each serial transfer operation; therefore, three consecutive read/write operations could be needed, depending on the mode. Figure 33 shows the connection diagram.
PIC16C6X/7X DVDD
AD5384
SPI/I2C RESET SDO DIN SCLK SYNC
04652-0-023
DR DT SCK TFS
AD5384
SPI/I2C RESET
RFS
SDI/RC4 SDO/RC5 SCK/RC3 RA1
SDO DIN SCLK SYNC
04652-0-021
Figure 35. AD5384-to-ADSP-2101/ADSP-2103 Interface
Figure 33. AD5384-to-PIC16C6x/7x Interface
Rev. A | Page 31 of 36
AD5384 APPLICATION INFORMATION
POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5384 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5384 is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only, a star ground point established as close to the device as possible. For supplies with multiple pins (AVDD, AVCC), these pins should be tied together. The AD5384 should have ample supply bypassing of 10 F in parallel with 0.1 F on each supply, located as close to the package as possible and ideally right up against the device. The 10 F capacitors are the tantalum bead type. The 0.1 F capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), like the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. The power supply lines of the AD5384 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals, such as clocks, should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. A ground line routed between the DIN and SCLK lines helps to reduce crosstalk between them (this is not required on a multilayer board because there is a separate ground plane, but separating the lines helps). It is essential to minimize noise on the VIN and REFIN lines. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to the ground plane while signal traces are placed on the solder side.
DATA REGISTER A
MONITOR FUNCTION
The AD5384 contains a channel monitor function that consists of a multiplexer addressed via the interface, allowing any channel output to be routed to this pin for monitoring using an external ADC. In channel monitor mode, VOUT39 becomes the MON_OUT pin, to which all monitored signals are routed. The channel monitor function must be enabled in the control register before any channels are routed to MON_OUT. contains the decoding information required to route any channel to MON_OUT. Selecting Channel Address 63 three-states MON_OUT. Figure 36 shows a typical monitoring circuit implemented using a 12-bit SAR ADC in a 6-lead SOT package. The controller output port selects the channel to be monitored, and the input port reads the converted data from the ADC.
AVCC VOUT0 DIN SYNC SCLK AVCC OUTPUT PORT
AD5384
AD7476 CS
VOUT39/MON_OUT VIN SCLK SDATA GND AGND VOUT38 DAC_GND SIGNAL_GND
04652-0-024
INPUT PORT
CONTROLLER
Figure 36. Typical Channel Monitoring Circuit
TOGGLE MODE FUNCTION
The toggle mode function allows an output signal to be generated using the LDAC control signal, which switches between two DAC data registers. This function is configured using the SFR control register as follows. A write with REG1 = REG0 = 0 and A5-A0 = 001100 specifies a control register write. The toggle mode function is enabled in groups of eight channels using Bits CR6 to CR2 in the control register (see Table 17). Figure 37 shows a block diagram of toggle mode implementation.
DAC REGISTER
DATA REGISTER B
14-BIT DAC
VOUT
INPUT INPUT DATA REGISTER
A/B
LDAC CONTROL INPUT
Figure 37. Toggle Mode Function
Rev. A | Page 32 of 36
04652-0-025
AD5384
Each of the 40 DAC channels on the AD5384 contains an A and B data register. Note that the B registers can be loaded only when toggle mode is enabled. The sequence of events when configuring the AD5384 for toggle mode is 1. 2. 3. 4. Enable toggle mode for the required channels via the control register. Load data to A registers. Load data to B registers. Apply LDAC.
THERMAL MONITOR FUNCTION
The AD5384 contains a temperature shutdown function to protect the chip if multiple outputs are shorted. The shortcircuit current of each output amplifier is typically 40 mA. Operating the AD5384 at 5 V leads to a power dissipation of 200 mW per shorted amplifier. With five channels shorted, this leads to an extra watt of power dissipation. For the 100-lead CSPBGA, the JA is typically 44C/W. The thermal monitor is enabled by the user via CR8 in the control register. The output amplifiers on the AD5384 are automatically powered down if the die temperature exceeds approximately 130C. After a thermal shutdown has occurred, the user can re-enable the part by executing a soft power-up if the temperature drops below 130C, or by turning off the thermal monitor function via the control register.
The LDAC is used to switch between the A and B registers in determining the analog output. The first LDAC configures the output to reflect the data in the A registers. This mode offers significant advantages if the user wants to generate a square wave at the output of all 40 channels, as might be required to drive a liquid crystal-based variable optical attenuator. In this case, the user writes to the control register and enables the toggle function by setting CR6 to CR2 = 1, thus enabling the five groups of eight for toggle mode operation. The user must then load data to all 40 A and B registers. Toggling LDAC sets the output values to reflect the data in the A and B registers. The frequency of the LDAC determines the frequency of the square wave output. Toggle mode is disabled via the control register. The first LDAC following the disabling of the toggle mode updates the outputs with the data contained in the A registers.
AD5384 IN A MEMS-BASED OPTICAL SWITCH
In their feed-forward control paths, MEMS based optical switches require high resolution DACs that offer high channel density with 14-bit monotonic behavior. The 40-channel, 14-bit AD5384 DAC satisfies these requirements. In the circuit in Figure 38, the 0 V to 5 V outputs of the AD5384 are amplified to achieve an output range of 0 V to 200 V, which is used to control actuators that determine the position of MEMS mirrors in an optical switch. The exact position of each mirror is measured using sensors. The sensor outputs are multiplexed into a high resolution ADC in determining the mirror position. The control loop is closed and driven by an ADSP-21065L, a 32-bit SHARC(R) DSP with an SPI-compatible SPORT interface. The ADSP-21065L writes data to the DAC, controls the multiplexer, and reads data from the ADC via the serial interface.
5V 0.01F
OUTPUT RANGE 0V-200V
REFOUT REFINA AVDD VOUT1 14-BIT DAC G = 50 ACTUATORS FOR MEMS MIRROR ARRAY SENSOR AND MULTIPLEXER 8-CHANNEL ADC (AD7856) OR SINGLE-CHANNEL ADC (AD7671)
14-BIT DAC
AD5384
VOUT40
G = 50
ADSP-21065L
Figure 38. AD5384 in a MEMS-Based Optical Switch
Rev. A | Page 33 of 36
04652-0-026
AD5384
OPTICAL ATTENUATORS
Based on its high channel count, high resolution, monotonic behavior, and high level of integration, the AD5384 is ideally targeted at optical attenuation applications used in dynamic gain equalizers, variable optical attenuators (VOA), and optical add-drop multiplexers (OADMs). In these applications, each wavelength is individually extracted using an arrayed wave guide; its power is monitored using a photodiode, transimpedance amplifier, and an ADC in a closed-loop control system.
ADD PORTS OPTICAL SWITCH 11 12 PHOTODIODES ATTENUATOR ATTENUATOR DWDM OUT AWG FIBRE 1n-1 1n ATTENUATOR ATTENUATOR DROP PORTS
The AD5384 controls the optical attenuator for each wavelength, ensuring that the power is equalized in all wavelengths before being multiplexed onto the fiber. This prevents information loss and saturation from occurring at amplification stages further along the fiber.
DWDM IN FIBRE AWG
TIA/LOG AMP (AD8304/AD8305)
AD5384, 40-CHANNEL, 14-BIT DAC
CONTROLLER
N:1 MULTIPLEXER
ADG731 (40:1 MUX)
16-BIT ADC
AD7671 (0-5V, 1MSPS)
Figure 39. OADM Using the AD5384 as Part of an Optical Attenuator
Rev. A | Page 34 of 36
04652-0-027
AD5384 OUTLINE DIMENSIONS
10.00 BSC SQ A1 CORNER INDEX AREA
12 11 10 9 87 6 5 43 21 A B C D E F G H J K L M
2.50 SQ
BALL A1 PAD CORNER TOP VIEW
8.80 BSC
BOTTOM VIEW
0.80 BSC 1.40 1.35 1.20 DETAIL A
0.65 REF 0.34 NOM 0.29 MIN
DETAILA
1.11 1.01 0.91
0.50* SEATING 0.45 PLANE 0.40 BALL DIAMETER *COMPLIANT TO JEDEC STANDARDS MO-205AC WITH THE EXCEPTION OF BALL DIAMETER.
0.12 MAX COPLANARITY
Figure 40. 100-Lead Chip Scale Package Ball Grid Array [CSP_BGA] (BC-100-2) Dimensions shown in millimeters
ORDERING GUIDE
Model AD5384BBC-5 AD5384BBC-5REEL7 AD5384BBC-3 AD5384BBC-3REEL7 Resolution 14 Bits 14 Bits 14 Bits 14 Bits Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C AVDD Range 4.5 V to 5.5 V 4.5 V to 5.5 V 2.7 V to 3.6 V 2.7 V to 3.6 V Output Channels 40 40 40 40 Linearity Error (LSB) 4 4 4 4 Package Description 100-Lead CSPBGA 100-Lead CSPBGA 100-Lead CSPBGA 100-Lead CSPBGA Package Option BC-100-2 BC-100-2 BC-100-2 BC-100-2
Rev. A | Page 35 of 36
AD5384 NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04652-0-10/04(A)
Rev. A | Page 36 of 36
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